1. Field of the Invention
The present invention relates to a power amplifier called a D-class amplifier (referred to as a “power amplifier apparatus” in this specification).
2. Description of the Related Art
A digital amplifier called a D-class amplifier has been known as an audio power amplifier apparatus. The D-class amplifier amplifies power by switching, which is configured in the manner shown in FIG. 11, for example.
Referring to FIG. 11, a digital audio signal Pin is supplied to a PWM (pulse width modulation) circuit 11 through an input terminal Tin and a clock signal having a predetermined frequency is supplied from a clock generating unit 12 to the PWM circuit 11, so that the digital audio signal Pin is converted to a pair of PWM signals PA and PB.
In this case, as shown in FIG. 13, pulse widths of the PWM signals PA and PB vary in accordance with a level of the digital audio signal Pin (instantaneous level at the time when the signal Pin is D/A converted (this is the same in the following description)). The pulse width of the PWM signal PA corresponds to the level of the digital audio signal Pin, whereas the pulse width of the PWM signal PB corresponds to a two's-complement number of the level of the digital audio signal Pin.
In the example shown in FIG. 13, rising edges of the PWM signals PA and PB are fixed to a start point of a cycle TC of the PWM signals PA and PB, and falling edges thereof change in accordance with the level of the digital audio signal Pin.
Further, a carrier frequency fc (=1/TC) of the PWM signals PA and PB is 16 times a sampling frequency fs of the digital audio signal Pin, as shown in “F” in FIG. 12. If fs=48 kHz, fc=16fs=16×48 kHz=768 kHz is satisfied.
The PWM signal PA from the PWM signal 11 is supplied to a drive circuit 13. Then, as shown in “A” in FIG. 12, a pair of driving pulse voltages (drive pulses) +PA and −PA, the former having the same level as the signal PA and the latter having an inverted level, are generated. These pulse voltages +PA and −PA are supplied to gates of a pair of switching devices, e.g., n-channel MOS-FETs (metal oxide semiconductor type field effect transistors) Q11 and Q12, respectively.
In this case, the FETs Q11 and Q12 form a push-pull circuit 15. A drain of the FET Q11 connects to a power supply terminal TPWR, a source thereof connects to a drain of the FET Q12, and a source of the FET Q12 connects to a ground. A stable DC (direct current) voltage +VDD is supplied as a power supply voltage to the power supply terminal TPWR. The voltage +VDD is 20 to 50 V, for example.
The source of the FET Q11 and the drain of the FET Q12 connect to one terminal of a speaker 19 through a low-pass filter 17 including a coil and a capacitor.
Also, the PWM signal PB is supplied from the PWM circuit 11 in the same manner as in the PWM signal PA. That is, the PWM signal PB is supplied to a drive circuit 14. Then, as shown in “B” in FIG. 12, a pair of driving pulse voltages (drive pulses) +PB and −PB, the former having the same level as the signal PB and the latter having an inverted level, are generated. These pulse voltages +PB and −PB are supplied to gates of a pair of n-channel MOS-FETs Q13 and Q14 forming a push-pull circuit 16, respectively.
A source of the FET Q13 and a drain of the FET Q14 connect to the other terminal of the speaker 19 through a low-pass filter 18 including a coil and a capacitor.
With this configuration, when +PA=“H” (high), −PA=“L” (low), the FET Q11 is turned ON, and the FET Q12 is turned OFF. Therefore, a voltage VA at a node between the FETs Q11 and Q12 is equal to the voltage +VDD, as shown in “C” in FIG. 12. On the other hand, when +PA=“L”, −PA=“H”, the FET Q11 is turned OFF, and the FET Q12 is turned ON. Therefore, the voltage VA is 0 (zero).
Likewise, when +PB=“H”, −PB=“L”, the FET Q13 is turned ON, and the FET Q14 is turned OFF. Therefore, a voltage VB at a node between the FETs Q13 and Q14 is equal to the voltage +VDD, as shown in “D” in FIG. 12. On the other hand, when +PB=“L”, −PB=“H”, the FET Q13 is turned OFF, and the FET Q14 is turned ON. Therefore, the voltage VB is 0 (zero).
During a period when VA=+VDD and VB=0, a current i flows from the node between the FETs Q11 and Q12 through the low-pass filter 17, the speaker 19, and the low-pass filter 18, to the node between the FETs Q13 and Q14, as shown in FIG. 11 and “E” in FIG. 12.
On the other hand, during a period when VA=0 and VB=+VDD, the current i flows in the opposite direction from the node between the FETs Q13 and Q14 through the low-pass filter 18, the speaker 19, and the low-pass filter 17, to the node between the FETs Q11 and Q12. However, the current i does not flow during periods when VA=VB=+VDD and when VA=VB=0. That is, the push-pull circuits 15 and 16 form a BTL (bridge tied load) circuit.
A period when the current i flows changes in accordance with a period when the PWM signals PA and PB are risen. Further, when the current i flows through the speaker 19, the current i is integrated by the low-pass filters 17 and 18. As a result, the current i flowing through the speaker 19 is an analog current corresponding to the level of the digital audio signal Pin and is a power-amplified current. In other words, power-amplified output is supplied to the speaker 19.
As described above, the circuit shown in FIG. 11 functions as a power amplifier apparatus. At this time, the FETs Q11 to Q14 amplify power by switching the power supply voltage +VDD in accordance with the input digital audio signal Pin. Therefore, a large output can be obtained with high efficiency.
Such a power amplifier apparatus is disclosed in Patent Documents 1 and 2 (Japanese Unexamined Patent Application Publication Nos. 2004-072707 and 2004-023216). In these Patent Documents, efforts are made to save power and enhance the performance.